Decimal multiplication using compressor based-BCD to binary converter
| Autor: | Rangababu Peesapati, Sasidhar Mukkamala, Pradeep Kumar Rathore |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
Adder
Computer Networks and Communications Computer science Field Programmable Gate Array (FPGA) 02 engineering and technology Biomaterials Gate count Application-specific integrated circuit 0202 electrical engineering electronic engineering information engineering Application Specific Integrated Circuit (ASIC) Hardware_ARITHMETICANDLOGICSTRUCTURES Field-programmable gate array Civil and Structural Engineering Electronic circuit Fluid Flow and Transfer Processes business.industry BCD to binary (BCD-Bin) converter Mechanical Engineering Compressor Binary-coded decimal Metals and Alloys 020206 networking & telecommunications Propagation delay Electronic Optical and Magnetic Materials lcsh:TA1-2040 Hardware and Architecture 020201 artificial intelligence & image processing Multiplier (economics) lcsh:Engineering (General). Civil engineering (General) business Computer hardware Hardware_LOGICDESIGN |
| Zdroj: | Engineering Science and Technology, an International Journal, Vol 21, Iss 1, Pp 1-6 (2018) |
| ISSN: | 2215-0986 |
| DOI: | 10.1016/j.jestch.2018.01.003 |
| Popis: | The objective of this work is to implement a scalable decimal to binary converter from 8 to 64 bits (i.e 2-digit to 16-digit) using parallel architecture. The proposed converters, along with binary coded decimal (BCD) adder and binary to BCD converters, are used in parallel implementation of Urdhva Triyakbhyam (UT)-based 32-bit BCD multiplier. To increase the performance, compressor circuits were used in converters and multiplier. The designed hardware circuits were verified by behavioural and post layout simulations. The implementation was carried out using Virtex-6 Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) with 90-nm technology library platforms. The results on FPGA shows that compressor based converters and multipliers produced less amount of propagation delay with a slight increase of hardware resources. In case of ASIC implementation, a compressor based converter delay is equivalent to conventional converter with a slight increase of gate count. However, the reduction of delay is evident in case of compressor based multiplier. |
| Databáze: | OpenAIRE |
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