CoreNEURON: Performance and Energy Efficiency Evaluation on Intel and Arm CPUs
| Autor: | Omar Awile, Marta Garcia-Gasulla, Ioannis Magkanaris, Joel Criado, Filippo Mantovani, Pramod Kumbhar |
|---|---|
| Přispěvatelé: | Barcelona Supercomputing Center |
| Jazyk: | angličtina |
| Předmět: |
supercomputing
Speedup intel Computer science 02 engineering and technology SIMD Instruction set Neural networks (Computer science) Energy efficiency 03 medical and health sciences 0302 clinical medicine SIMD (Computer architecture) Computer cluster arm Neuronal networks 0202 electrical engineering electronic engineering information engineering NEURON Informàtica::Arquitectura de computadors::Arquitectures paral·leles [Àrees temàtiques de la UPC] energy efficiency mechanisms 020203 distributed computing Processament en paral·lel (Ordinadors) Supercomputing Intel simulation Supercomputer neuron performance evaluation ARM architecture simd Computer architecture Performance evaluation Arm neuronal networks High performance computing 030217 neurology & neurosurgery |
| Zdroj: | 2020 IEEE International Conference on Cluster Computing (CLUSTER) UPCommons. Portal del coneixement obert de la UPC Universitat Politècnica de Catalunya (UPC) CLUSTER |
| DOI: | 10.1109/cluster49012.2020.00077 |
| Popis: | The simulation of detailed neuronal circuits is based on computationally expensive software simulations and requires access to a large computing cluster. The appearance of new Instruction Set Architectures (ISAs) in most recent High-Performance Computing (HPC) systems, together with the layers of system software and complex scientific applications running on top of them, makes the performance and power figures challenging to evaluate. In this paper, we focus on evaluating CoreNEURON on two HPC systems powered by Intel and Arm architectures. CoreNEURON is a computational engine of the widely used NEURON simulator adapted to run on emerging architectures while maintaining compatibility with existing NEURON models developed by the neuroscience community. The evaluation is based on the analysis of the dynamic instruction mix on two versions of CoreNEURON. It focuses on the performance gain obtained by exploiting the Single Instruction Multiple Data (SIMD) unit and includes energy measurements. Our results show that using a tool for increasing data-level parallelism (ISPC) boosts the performance up to 2× independently on the ISA. Its combination with vendor-specific compilers can further speed up the neural simulation time. Also, the performance/price ratio is higher for Arm-based systems than for Intel ones making them more cost-efficient keeping the same usability level of other HPC systems. This work is partially supported by the Spanish Government (SEV-2015-0493), by the Spanish Ministry of Science and Technology (TIN2015-65316-P), by the Generalitat de Catalunya (2017-SGR-1414), by the European Mont-Blanc 3 project (GA n. 671697), Human Brain Project SGA2 (GA n. 785907), and POP CoE (GA n. 824080). |
| Databáze: | OpenAIRE |
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