Implementation and Design of FIR Filters using Verilog HDL and FPGA

Autor:	Ramesh, Akshitha V, Kumar, Apeksha Ravi, Iyengar, Amulya S, B, Lekha Yadav
Jazyk:	angličtina
Rok vydání:	2020
Předmět:	Digital Filter Linear phase FPGA kit VLSI systems FIR filter Hardware_ARITHMETICANDLOGICSTRUCTURES MAC operation Impulse Response
Zdroj:	Perspectives in Communication, Embedded-systems and Signal-processing-PiCES; Vol. 4 No. 5 (2020): Issue 5-August 2020; 85-88
ISSN:	2566-932X
DOI:	10.5281/zenodo.4018834
Popis:	Digital filters play a major role in Very Large-Scale Integration Technology (VLSI), as most VLSI systems use addition as an integral operation. One such filter is FIR filter, whose basic implementation is achieved by adders. This paper mainly aims at designing a Moving Average 4-tap FIR filter using Verilog HDL and is implemented using Xilinx software and Spartan 6 FPGA kit with the concepts of Multiply and Accumulate (MAC) operation and convolution. To view and download the paper for free, visit: http://pices-journal.com/ojs/index.php/pices/article/view/220
Databáze:	OpenAIRE
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