Test planning and test access mechanism design for stacked chips using ILP
| Autor: | Breeta Sengupta, Erik Larsson |
|---|---|
| Rok vydání: | 2014 |
| Předmět: |
Engineering
business.industry Test Scheduling Test Time Scan chain DfT (Design for test) Test compression Integrated circuit Electrical Engineering Electronic Engineering Information Engineering Chip law.invention Computer architecture Built-in self-test law Wafer testing Test Architecture Integer Linear Programming (ILP) Test plan business 3D Stacked Integrated Circuit (SIC) Integer programming Computer hardware Wrapper Chain |
| Zdroj: | VTS pp 1-6 (2014) |
| ISSN: | 1093-0167 |
| DOI: | 10.1109/vts.2014.6818764 |
| Popis: | In this paper we propose a scheme for test planning and test access mechanism (TAM) design for stacked integrated circuits (SICs) that are designed in a core-based manner. Our scheme minimizes the test cost, which is given as the weighted sum of the test time and the TAM width. The test cost is evaluated for a test flow that consists of a wafer sort test of each individual chip and a package test of the complete stack of chips. We use an Integer Linear Programming (ILP) model to find the optimal test cost. The ILP model is implemented on several designs constructed from ITC’02 benchmarks. The experimental results show significant reduction in test cost compared to when using schemes, which are optimized for non-stacked chips. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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