Performance and Modeling of Si-Nanocrystal Double-Layer Memory Devices With High- $k$ Control Dielectrics
| Autor: | G. Gay, G. Molas, M. Bocquet, E. Jalaguier, M. Gely, L. Masarotto, J. P. Colonna, H. Grampeix, F. Martin, P. Brianceau, V. Vidal, R. Kies, T. Baron, G. Ghibaudo, B. De Salvo |
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| Přispěvatelé: | Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS) |
| Rok vydání: | 2012 |
| Předmět: |
010302 applied physics
Double layer (biology) Materials science Silicon business.industry chemistry.chemical_element Nanotechnology 02 engineering and technology 021001 nanoscience & nanotechnology 01 natural sciences Electronic Optical and Magnetic Materials Nanocrystal Stack (abstract data type) chemistry Logic gate 0103 physical sciences Optoelectronics [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Electrical and Electronic Engineering 0210 nano-technology business Layer (electronics) ComputingMilieux_MISCELLANEOUS Quantum tunnelling High-κ dielectric |
| Zdroj: | IEEE Transactions on Electron Devices IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2012, 59 (4), pp.933-940. ⟨10.1109/TED.2012.2182769⟩ IEEE Transactions on Electron Devices, 2012, 59 (4), pp.933-940. ⟨10.1109/TED.2012.2182769⟩ |
| ISSN: | 1557-9646 0018-9383 |
| DOI: | 10.1109/ted.2012.2182769 |
| Popis: | In this paper, memory devices integrating a double layer of silicon nanocrystals (Si-ncs) as a trapping medium and a HfAlO-based control dielectrics are presented. We will show that the use of two stacked Si-nc layers significantly improves the memory window compared with the single Si-nc layer devices, without introducing anomalies on the charging dynamics. Then, we also evaluate the potential use of a hybrid Si-nc double-layer/SiN layer charge trapping stack. These devices show a good memory window in a Fowler-Nordheim (FN)/FN mode and a good retention (>; 3 V after ten years) with small activation energy (0.35 eV up to 200 °C), thus showing promise for future high-temperature memory applications. A model implying valence-band electron tunneling and a floating-gate-like approximation is used to explain the memory window improvement of the Si-nc double-layer memory devices. |
| Databáze: | OpenAIRE |
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