A universal spintronic technology based on Multifunctional Standardized Stack
| Autor: | Mehdi B. Tahoori, Guillaume Patrigeon, Guillaume Prenat, Lionel Torres, Rajendra Bishnoi, G. Di Pendina, Sophiane Senni, Pascal Benoit, Sarath Mohanachandran Nair |
|---|---|
| Přispěvatelé: | Karlsruher Institut für Technologie (KIT), ADAptive Computing (ADAC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), SPINtronique et TEchnologie des Composants (SPINTEC), Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche Interdisciplinaire de Grenoble (IRIG), Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Fondamentale (CEA) (DRF (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Grenoble Alpes (UGA), European Project: 687973,H2020,H2020-ICT-2015,GREAT(2016) |
| Jazyk: | angličtina |
| Rok vydání: | 2020 |
| Předmět: |
010302 applied physics
Magnetoresistive random-access memory Electronic system-level design and verification Hardware_MEMORYSTRUCTURES Computer science Process (computing) Process design Fault tolerance 02 engineering and technology 01 natural sciences 020202 computer hardware & architecture CMOS Computer architecture 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Electronic design automation [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics AND gate |
| Zdroj: | 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) DATE 2020-23rd Design, Automation and Test in Europe Conference and Exhibition DATE 2020-23rd Design, Automation and Test in Europe Conference and Exhibition, Mar 2020, Grenoble, France. pp.394-399, ⟨10.23919/DATE48585.2020.9116321⟩ DATE |
| DOI: | 10.23919/DATE48585.2020.9116321⟩ |
| Popis: | International audience; The goal of the GREAT RIA project is to cointegrate multiple functions like sensors ("Sensing"), RF emitters or receivers ("Communicating") and logic/memory ("Processing/Storing") together within CMOS technology by adapting the Spin-Transfer Torque Magnetic Tunnel Junction (STT-MTJ), elementary constitutive cell of the MRAM memories, to a single baseline technology. Based on the STT unique set of performances (non-volatility, high speed, infinite endurance and moderate read/write power), GREAT will achieve the same goal as heterogeneous integration of devices but in a much simpler way. This will lead to a unique STT-MTJ cell technology called Multifunctional Standardized Stack (MSS). This paper presents the lessons learned in the project from the technology, compact modeling, process design kit, standard cells, as well as memory and system level design evaluation and exploration. The proposed technology and toolsets are giant leaps towards heterogeneous integrated technology and architectures for IoT. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|