Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation
| Autor: | Sunwoo Kim, Sungkyung Park, Jooho Wang, Chester Park |
|---|---|
| Rok vydání: | 2021 |
| Předmět: |
Finite impulse response
Computer Networks and Communications Orthogonal frequency-division multiplexing Computer science digital front-end lcsh:TK7800-8360 carrier aggregation 02 engineering and technology CIC Application-specific integrated circuit FIR filter 0202 electrical engineering electronic engineering information engineering Electronic engineering Electrical and Electronic Engineering Field-programmable gate array FPGA Decimation Cascaded integrator–comb filter decimation ASIC lcsh:Electronics fractional sample-rate conversion 020206 networking & telecommunications LTE CMOS Hardware and Architecture Control and Systems Engineering Filter (video) Signal Processing digital mixer Adjacent channel 020201 artificial intelligence & image processing Farrow interpolator |
| Zdroj: | Electronics Volume 10 Issue 3 Electronics, Vol 10, Iss 231, p 231 (2021) |
| ISSN: | 2079-9292 |
| Popis: | A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA). |
| Databáze: | OpenAIRE |
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