| Popis: |
A study of the impact of dimension and temperature on a state of the art 4H-SiC power vertical DMOSFET has been carried out using drift-diffusion calculations in conjunction with electrical characterizations to extract physical parameters and doping profiles in a 6 μm channel length device. The model presented in this paper includes the effect of trapping in the channel/oxide interface. Using these parameters, the performance of corresponding lateral and vertical scaled devices are studied. Electrothermal simulations showing self-heating effects are also carried out. The results are qualitatively discussed with the help of an analytical physical model, which considers the interplay between the different device resistances. At low drain bias, the drain current is increased by 42.86% (I D = 5 A at V G = 20 V) when reducing the dimension vertically, whereas it is decreased by 28.57% (I D = 2.5 A at V G = 20 V) when reducing the dimension laterally. These effects are enhanced at high drain bias. In addition, the effect of dimension reduction for breakdown voltage, electric field and impact ionization is investigated. A substantial reduction in breakdown voltage was found when the vertical dimensions were decreased as compared to the lateral dimensions. |
