RISC-V Extension for Lightweight Cryptography
| Autor: | Abdelmalek Si Merabet, Jean-Luc Danger, Tarik Graba, Etienne Tehrani |
|---|---|
| Přispěvatelé: | Laboratoire Traitement et Communication de l'Information (LTCI), Institut Mines-Télécom [Paris] (IMT)-Télécom Paris, Département Communications & Electronique (COMELEC), Télécom ParisTech, Secure and Safe Hardware (SSH), Institut Mines-Télécom [Paris] (IMT)-Télécom Paris-Institut Mines-Télécom [Paris] (IMT)-Télécom Paris |
| Jazyk: | angličtina |
| Rok vydání: | 2020 |
| Předmět: |
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]
business.industry Computer science [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic 020207 software engineering Cryptography 02 engineering and technology [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation [SPI.TRON]Engineering Sciences [physics]/Electronics [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR] Embedded system RISC-V 0202 electrical engineering electronic engineering information engineering [INFO.INFO-DL]Computer Science [cs]/Digital Libraries [cs.DL] 020201 artificial intelligence & image processing Execution unit Reference architecture Latency (engineering) business Throughput (business) ComputingMilieux_MISCELLANEOUS Block cipher Block (data storage) |
| Zdroj: | 2020 23rd Euromicro Conference on Digital System Design (DSD) 2020 23rd Euromicro Conference on Digital System Design (DSD), Aug 2020, Kranj, Slovenia. pp.222-228, ⟨10.1109/DSD51259.2020.00045⟩ DSD |
| DOI: | 10.1109/DSD51259.2020.00045⟩ |
| Popis: | Lightweight Cryptography (LWC) is suitable for IoTs which require a high level of security while keeping a low complexity. Many lightweight cryptographic algorithms have been proposed to satisfy these requirements. But there is currently no emerging standard concerning the symmetric block ciphering, as every algorithm has its own advantage. For instance one can be optimized for low latency, another one for low complexity but requires more rounds to be cryptographically secure to the detriment of throughput. Hence, a processor able to cope with all the algorithms should be ideal to provide agility, performance and security while keeping an affordable complexity. We present in this paper a specific execution unit of the RISC-V processor which is able to run the most common lightweight 64-bit block ciphers. The gain in performance can reach over a hundred compared to the reference architecture. The acceleration takes advantage of five specific instructions which can easily be adapted to the execution unit of a VexRiscv architecture. The complexity can double when implementing the new execution unit, but provide a high degree of agility and performance when executing most of lightweight cryptographic implementations. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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