A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load
| Autor: | Tetsuya Iizuka, Kunihiro Asada, Toru Nakura, Naoki Ojima |
|---|---|
| Přispěvatelé: | The University of Tokyo (UTokyo), Fukuoka University, VLSI Design and Education Center, Nicola Bombieri, Graziano Pravadelli, Masahiro Fujita, Todd Austin, Ricardo Reis, TC 10, WG 10.5 |
| Jazyk: | angličtina |
| Rok vydání: | 2018 |
| Předmět: |
Physics
Low-dropout regulator Comparator business.industry 020208 electrical & electronic engineering Electrical engineering 02 engineering and technology Phase detector 020202 computer hardware & architecture CMOS 0202 electrical engineering electronic engineering information engineering Inverter Verilog [INFO]Computer Science [cs] business computer Voltage reference computer.programming_language Voltage |
| Zdroj: | IFIP Advances in Information and Communication Technology 26th IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip (VLSI-SoC) 26th IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip (VLSI-SoC), Oct 2018, Verona, Italy. pp.1-13, ⟨10.1007/978-3-030-23425-6_1⟩ VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms ISBN: 9783030234249 VLSI-SoC (Selected Papers) |
| DOI: | 10.1007/978-3-030-23425-6_1⟩ |
| Popis: | A synthesizable digital LDO implemented with standard-cell-based digital design flow is proposed. The difference between output and reference voltages is converted into delay difference using inverter chains as voltage-controlled delay lines, then compared in the time-domain. Since the time-domain difference is straightforwardly captured by a simple DFF-based phase detector, the proposed LDO does not need an analog voltage comparator, which requires careful manual design. All the components in the LDO can be described with Verilog codes based on their specifications, and placed-and-routed with a commercial EDA tool. This automated layout design relaxes the burden and time of implementation, and enhances process portability. The proposed LDO implemented in a 65 nm standard CMOS technology occupies 0.015 mm\(^2\) area. With 10.4 MHz internal clock, the tracking response of the LDO to 200 mV switching in the reference voltage is \(\sim \)4.5 \(\upmu \)s and the transient response to 5 mA change in the load current is \(\sim \)6.6 \(\upmu \)s. At 10 mA load current, the quiescent current consumed by the LDO core is as low as 35.2 \(\upmu \)A, which leads to 99.6% current efficiency. |
| Databáze: | OpenAIRE |
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