Architecture of the multi-tap-delay-line time-interval measurement module implemented in FPGA device

Autor:	Marek Zieliński, Maciej Gurski, Dariusz Chaberski
Jazyk:	angličtina
Rok vydání:	2013
Předmět:	Engineering business.industry Mechanical Engineering education High resolution Total measurement Level of measurement Duty cycle Electrical and Electronic Engineering Line (text file) Architecture Field-programmable gate array business Instrumentation Computer hardware
Zdroj:	Instrumentation viewpoint; 2013: Núm.: 14 UPCommons. Portal del coneixement obert de la UPC Universitat Politècnica de Catalunya (UPC)
Popis:	This paper describes the architecture of a Multi-Tap-Delay-Line (MTDL) time-interval measurement module of high resolution implemented in a single FPGA device. The new architecture of the measurement module enables to collect sixteen time-stamps during a single measuring cycle. It means that the measured time-interval can be precisely interpolated from the collection of the sixteen time-stamps after each measuring cycle. Such architecture of the measurement module leads directly to an increased resolution, to a limited total measurement time and a decreased duty cycle of the measurement instrument.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1ccddd1629b8cd91dfe79f8d8032f81a https://hdl.handle.net/2099/15257 Zobrazit plný text záznamu