Stacked-Wires FETs for Advanced CMOS Scaling

Autor:	S. Barraud, V. Lapras, M.P. Samson, B. Previtali, J.M. Hartmann, N. Rambal, C. Vizioz, V. Loup, C. Comboroure, F. Triozon, N. Bernier, D. Cooper, M. Vinet
Přispěvatelé:	Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), European Project: 688101,H2020,H2020-ICT-2015,SUPERAID7(2016), BARRAUD, SYLVAIN, Stability Under Process Variability for Advanced Interconnects and Devices Beyond 7 nm node - SUPERAID7 - - H20202016-01-01 - 2018-12-31 - 688101 - VALID
Rok vydání:	2017
Předmět:	[SPI]Engineering Sciences [physics] Materials science [SPI] Engineering Sciences [physics] business.industry Hardware_INTEGRATEDCIRCUITS Optoelectronics Hardware_PERFORMANCEANDRELIABILITY business Cmos scaling Hardware_LOGICDESIGN
Zdroj:	2017 International Conference on Solid State Devices and Materials (SSDM 2017) 2017 International Conference on Solid State Devices and Materials (SSDM 2017), Sep 2017, Sendaï, Japan
DOI:	10.7567/ssdm.2017.e-2-01
Popis:	International audience; We present recent progress on vertically stacked-wires MOSFETs with a replacement metal gate process for CMOS scaling beyond FinFET technology. Key technological challenges (such as 3D integration process including inner spacer, mobility, and strain engineering) will be discussed in relation to recent research results.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1a52597d3edf5f61ac25e77775b1678e https://doi.org/10.7567/ssdm.2017.e-2-01 Zobrazit plný text záznamu