AivoTTA
| Autor: | Ijzerman, Jos, Viitanen, Timo, Jääskeläinen, Pekka, Kultala, Heikki, Lehtonen, Lasse, Peemen, Maurice, Corporaal, Henk, Takala, Jarmo, Mudge, Trevor, Pnevmatikatos, Dionisios N. |
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| Přispěvatelé: | Tampere University, Pervasive Computing, Electrical Engineering, Electronic Systems |
| Jazyk: | angličtina |
| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Computer science business.industry Clock rate Cognitive neuroscience of visual object recognition 02 engineering and technology computer.software_genre 113 Computer and information sciences 01 natural sciences Convolutional neural network Object detection 020202 computer hardware & architecture 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Hardware acceleration SIMD Compiler SDG 7 - Affordable and Clean Energy business computer Computer hardware SDG 7 – Betaalbare en schone energie Efficient energy use |
| Zdroj: | SAMOS Proceedings-2018 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2018, 28-37 STARTPAGE=28;ENDPAGE=37;TITLE=Proceedings-2018 International Conference on Embedded Computer Systems |
| Popis: | Battery driven intelligent cameras used, e.g., in police operations or pico drone based surveillance require good object detection accuracy and low energy consumption at the same time. Object recognition algorithms based on Convolutional Neural Networks (CNN) currently produce the best accuracy, but require relatively high computational power. General purpose CPU and GPU implementations of CNN-based object recognition provide flexibility and performance, but this flexibility comes at a high energy cost. Fixed function hardware acceleration of CNNs provides the best energy efficiency, with a trade-off in reduced flexibility. This paper presents AivoTTA, a flexible and energy efficient CNN accelerator with a SIMD Transport-Triggered Architecture that is programmable in C and OpenCL C. The proposed accelerator makes use of smart memory access patterns and fusion of layers to greatly reduce the number of memory transfers and improve energy efficiency. The accelerator was synthesized using 28 nm ASIC technology for different supply voltages and clock frequencies. The most power efficient design points consume 11.3 mW for an object recognition network running 16 GOPS at 400 MHz. The maximum clock frequency is 1.4 GHz. With the maximum clock, the accelerator consumes 116 mW for an effective 57 GOPS. To the best of our knowledge, it is the most energy efficient compiler programmable CNN accelerator published. acceptedVersion |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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