Decimal multiplication in FPGA with a novel decimal adder/subtractor
| Autor: | Horácio C. Neto, Mário P. Véstias |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2021 |
| Předmět: |
Adder
Industrial engineering. Management engineering Computer science MathematicsofComputing_NUMERICALANALYSIS Binary number Data_CODINGANDINFORMATIONTHEORY 02 engineering and technology T55.4-60.8 decimal multiplication Operand Decimal Theoretical Computer Science ComputingMethodologies_SYMBOLICANDALGEBRAICMANIPULATION Subtractor 0202 electrical engineering electronic engineering information engineering Hardware_ARITHMETICANDLOGICSTRUCTURES Arithmetic FPGA Numerical Analysis Decimal multiplication decimal adder parallel multiplication QA75.5-76.95 Excess-3 coding Numerical digit 020202 computer hardware & architecture Adder–subtractor Computational Mathematics Computational Theory and Mathematics Electronic computers. Computer science Decimal adder parallel multiplication 020201 artificial intelligence & image processing Multiplication excess-3 coding Hardware_LOGICDESIGN |
| Zdroj: | Repositório Científico de Acesso Aberto de Portugal Repositório Científico de Acesso Aberto de Portugal (RCAAP) instacron:RCAAP Algorithms, Vol 14, Iss 198, p 198 (2021) |
| Popis: | Financial and commercial data are mostly represented in decimal format. To avoid errors introduced when converting some decimal fractions to binary, these data are processed with decimal arithmetic. Most processors only have hardwired binary arithmetic units. So, decimal operations are executed with slow software-based decimal arithmetic functions. For the fast execution of decimal operations, dedicated hardware units have been proposed and designed in FPGA. Decimal multiplication is found in most decimal-based applications and so its optimized design is very important for fast execution. In this paper two new parallel decimal multipliers in FPGA are proposed. These are based on a new decimal adder/subtractor also proposed in this paper. The new decimal multipliers improve state-of-the-art parallel decimal multipliers. Compared to previous architectures, implementation results show that the proposed multipliers achieve 26% better area and 12% better performance. Also, the new decimal multipliers reduce the area and performance gap to binary multipliers and are smaller for 32 digit operands. |
| Databáze: | OpenAIRE |
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