| Autor: |
Vishvanath Janjirala, Noor Mahammad S, M Neeharika, L Hemanth Krishna, Sreehari Veeramachaneni |
| Jazyk: |
angličtina |
| Rok vydání: |
2021 |
| Předmět: |
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| Zdroj: |
IET Computers & Digital Techniques, Vol 15, Iss 1, Pp 12-19 (2021) |
| ISSN: |
1751-8601 |
| Popis: |
This paper proposes an efficient approach to design high‐speed, accurate multipliers. The proposed multiplier design uses the proposed efficient 15:4 counter for the partial product reduction stage. This proposed 15:4 counter is designed using a novel 5:3 counter. The proposed 5:3 counter uses input re‐ordering circuitry at the input side. As a result, the number of output combinations can be reduced to 18 from 32. As a result, the circuit complexity reduces. The proposed 5:3 counter and 15:4 counter are on an average 28% and 19% improvement in the power delay product compared with the existing designs. The 16‐bit multiplier designed using 5:3 and 15:4 counters is an average 22.5% improvement in power delay product compared with the existing designs. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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