Toward multi-layer holistic evaluation of system designs
| Autor: | Kleanthous, Marios, Sazeides, Yiannakis, Ozer, E., Nicopoulos, Chrysostomos A., Nikolaou, Panagiota, Hadjilambrou, Zacharias, Kleanthous, Marios M. |
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| Přispěvatelé: | Nicopoulos, Chrysostomos A. [0000-0001-6389-6068] |
| Rok vydání: | 2016 |
| Předmět: |
Design
Process (engineering) Design space exploration Computer science Reliability (computer networking) Integration Chip Systems analysis Servers 02 engineering and technology Datacenter 01 natural sciences Server Evaluation metrics 0103 physical sciences Design-space exploration 0202 electrical engineering electronic engineering information engineering System on a chip 010302 applied physics Holistic evaluations Total cost of ownership 020202 computer hardware & architecture Reliability engineering Three dimensional integrated circuits Computer architecture Hardware and Architecture Integrated circuit design Holistic evaluation Metric (unit) |
| Zdroj: | IEEE Computer Architecture Letters IEEE Comput.Archit.Lett. |
| Popis: | The common practice for quantifying the benefit(s) of design-time architectural choices of server processors is often limited to the chip- or server-level. This quantification process invariably entails the use of salient metrics, such as performance, power, and reliability, which capture - in a tangible manner - a designs overall ramifications. This paper argues for the necessity of a more holistic evaluation approach, which considers metrics across multiple integration levels (chip, server and datacenter). In order to facilitate said comprehensive evaluation, we utilize an aggregate metric, e.g. the Total Cost of Ownership (TCO), to harness the complexly of comparing multiple metrics at multiple levels. We motivate our proposition for holistic evaluation with a case study that compares a 2D processor to a 3D processor at various design integration levels. We show that while a 2D processor is clearly the best choice at the processor level, the conclusion is reversed at the data-center level, where the 3D processor becomes a better choice. This result emanates mainly from the performance benefits of processor-DRAM 3D integration, and the ability to amortize (at the datacenter-level) the higher 3D per-server cost and lower reliability by requiring fewer 3D servers to match the same performance. © 2015 IEEE. 15 1 58 61 |
| Databáze: | OpenAIRE |
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