Process Modules for High-Density Interconnects in Panel-Level Packaging
| Autor: | Jordan Kossev, R. Kahle, Marc Kunz, Friedrich-Leonhard Schein, Mathias Pentz, Tobias Muller, Tim Kunz, Andreas Ostmann, Michael Dietterle |
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| Přispěvatelé: | Publica |
| Rok vydání: | 2020 |
| Předmět: |
010302 applied physics
Microvia Materials science Plasma etching business.industry 020206 networking & telecommunications 02 engineering and technology 01 natural sciences Aspect ratio (image) Industrial and Manufacturing Engineering Electrical contacts Electronic Optical and Magnetic Materials Printed circuit board Resist 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Optoelectronics Wafer Redistribution layer Electrical and Electronic Engineering business |
| Zdroj: | IEEE Transactions on Components, Packaging and Manufacturing Technology. 10:5-10 |
| ISSN: | 2156-3985 2156-3950 |
| DOI: | 10.1109/tcpmt.2019.2956325 |
| Popis: | Advanced packaging technologies like wafer-level fan-out and 3-D system-in-package (3-D SIP) are rapidly penetrating the market of electronic components. For cost reduction, one approach is the migration of processes from wafer to panel format, called panel-level packaging (PLP). In a consortium of partners from industry and research, advanced technologies for PLP are developed. The project aims for an integrated process flow for 3-D SIPs with chips embedded into an organic laminate matrix. At first, 6 mm $\times 6$ mm chips (100 $\mu \text{m}$ thickness) with Cu bumps (25- $\mu \text{m}$ height, 110- $\mu \text{m}$ pitch) are placed into cavities of a printed circuit board (PCB) core layer. They are embedded by vacuum lamination of thin organic films. The core is equipped with fiducials for local alignment and provides handling robustness. Developments aim for a final panel size of 600 mm $\times600$ mm (here 227 mm $\times305$ mm demonstrated). Onto the contact side of embedded chips, a 25- $\mu \text{m}$ dielectric film is applied. The copper bumps are subsequently opened by plasma etching. By sputtering and electroplating of Cu, electrical contacts to the chips are formed without via opening. High-aspect-ratio vias as an element for vertical interconnects are formed by UV laser drilling. At via diameters of 17 $\mu \text{m}$ , a drill hole depth of 74 $\mu \text{m}$ was achieved (aspect ratio 4.4:1). Using a newly developed electrolyte, microvia filling was achieved for aspect ratios up to 4:1. With a newly developed direct imaging (DI) machine, 4- $\mu \text{m}$ structures in a 7- $\mu \text{m}$ dry film photoresist are formed. Adaptive imaging of a redistribution layer was realized. |
| Databáze: | OpenAIRE |
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