Hardware Design and Implementation of Adaptive Multiple Transforms for the Versatile Video Coding Standard
| Autor: | Fatma Belghith, Nouri Masmoudi, Ahmed Kammoun, Jean-Francois Nezan, Wassim Hamidouche |
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| Přispěvatelé: | Institut d'Électronique et des Technologies du numéRique (IETR), Université de Nantes (UN)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Laboratoire d'électronique et des technologies de l'Information [Sfax] (LETI), École Nationale d'Ingénieurs de Sfax | National School of Engineers of Sfax (ENIS), DOS0061463/00, Bpifrance Financement, Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Nantes Université (NU)-Université de Rennes 1 (UR1) |
| Rok vydání: | 2018 |
| Předmět: |
Adaptive Multiple Transform
business.industry Computer science [INFO.INFO-MM]Computer Science [cs]/Multimedia [cs.MM] 020206 networking & telecommunications 02 engineering and technology Future Video Coding [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing Discrete sine transform Pipeline 0202 electrical engineering electronic engineering information engineering Media Technology Discrete cosine transform 020201 artificial intelligence & image processing Electrical and Electronic Engineering DSP business Field-programmable gate array Encoder FPGA Computer hardware Digital signal processing Hardware Implementa- tion Coding (social sciences) |
| Zdroj: | IEEE Transactions on Consumer Electronics IEEE Transactions on Consumer Electronics, Institute of Electrical and Electronics Engineers, 2018, 64 (4), pp.424-432. ⟨10.1109/TCE.2018.2875528⟩ IEEE Transactions on Consumer Electronics, 2018, 64 (4), pp.424-432. ⟨10.1109/TCE.2018.2875528⟩ |
| ISSN: | 1558-4127 0098-3063 |
| DOI: | 10.1109/tce.2018.2875528 |
| Popis: | Versatile video coding is the next generation video coding standard expected by the end of 2020. Several new contributions have been proposed to enhance the coding efficiency beyond the high efficiency video coding standard. One of these tools is the adaptive multiple transform (AMT) as a new approach of the transform core design. The AMT involves five discrete cosine transform/discrete sine transform types with larger and more flexible partitioning block sizes. However, the AMT coding efficiency comes with the cost of higher computational complexity, especially at the encoder side. In this paper, a efficient pipelined hardware implementation of the AMT including the five types of sizes $4\times 4$ , $8\times 8$ , $16\times 16$ and $32\times 32$ is proposed. The architecture design takes advantage of the internal software/hardware resources of the target field-programmable gate array device such as library of parametrized modules core intellectual properties and digital signal processing blocks. The proposed 1-D 32-point AMT design allows to process 4K video at 44 frames/s. A unified 2-D implementation of the 4, 8, 16, and 32-point AMT design is also presented.The implementation takes into account all the asymmetric 2-D block size combinations from 4 to 32. The 2-D architecture design is able to sustain 2K video coding at 50 frames/s with an operational frequency up to 147 MHz. |
| Databáze: | OpenAIRE |
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