Energy efficient fine-grain reconfigurable hardware

Autor:	Dimitrios Soudris, V. Kalenteridis, H. Pournara, Nikolaos Vassiliadis, Ilias Pappas, Stylianos Siskos, Spiridon Nikolaidis
Rok vydání:	2004
Předmět:	Engineering CMOS Logic block business.industry Logic gate Hardware_INTEGRATEDCIRCUITS Electronic engineering Energy consumption Integrated circuit design business Field-programmable gate array Reconfigurable computing Efficient energy use
Zdroj:	Scopus-Elsevier
DOI:	10.1109/melcon.2004.1346810
Popis:	In this paper a novel energy efficient FPGA architecture was designed and simulated in STM 0.18/spl mu/m CMOS technology. The parameters of the configurable logic block architecture have been determined in order to minimize energy consumption. Circuit level low power design techniques are also applied for further reducing energy consumption. In addition, an exploration for the optimum, in terms of energy, delay and area, interconnection routing switches size has been performed.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0e7c7da57f80213f5b5eb8a8838490a9 https://doi.org/10.1109/melcon.2004.1346810 Zobrazit plný text záznamu