Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects With Metal Vias
| Autor: | Kaustav Banerjee, Kunjesh Agashiwala, Dujiao Zhang, Junkai Jiang, Kamyar Parto, Chao-Hui Yeh |
|---|---|
| Rok vydání: | 2021 |
| Předmět: |
Integrated circuit interconnections
Materials science interconnects Resistance Interconnect technology Hardware_PERFORMANCEANDRELIABILITY Dielectric 01 natural sciences Electromigration electromigration law.invention Metal Reliability (semiconductor) law 0103 physical sciences Hardware_INTEGRATEDCIRCUITS Silicon compounds graphene capping-layer Electrical and Electronic Engineering CMOS-compatible subtractive etching Applied Physics 010302 applied physics reliability Substrates business.industry Graphene self-heating Wires solid-phase diffusion multi-level Electronic Optical and Magnetic Materials doped multilayer graphene Metals visual_art visual_art.visual_art_medium Optoelectronics Stress conditions dual-damascene business Cmos compatible |
| Zdroj: | IEEE Transactions on Electron Devices, vol 68, iss 4 |
| ISSN: | 1557-9646 0018-9383 |
| Popis: | Doped-multilayer-graphene (DMLG) interconnects employing the subtractive-etching (SE) process have opened a new pathway for designing interconnects at advanced technology nodes, where conventional metal wires suffer from significant resistance increase, self-heating (SH), electromigration (EM), and various integration challenges. Even though single-level scaled graphene wires have been shown to possess better performance and reliability with respect to dual-damascene (DD) and SE-enabled metal wires, a multi-level graphene interconnect technology (with vias) has remained elusive, which is of paramount importance for its integration in future technology nodes. This work, for the first time, addresses that need by engineering a CMOS-compatible solid-phase growth technique to yield large-area multilayer graphene (MLG) on dielectric (SiO2) and metal (Cu) substrates and subsequently demonstrating multi-level MLG interconnects with metal vias. Using rigorous theoretical and experimental analyses, we demonstrate that multi-level MLG interconnects with metal vias undergo < 2% change in the via resistance under accelerated stress conditions, demonstrating its superior reliability against SH and EM, making them ideal candidates for sub-10 nm nodes. |
| Databáze: | OpenAIRE |
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