Semiconductor Chip Electrical Interconnection and Bonding by Nano-Locking with Ultra-Fine Bond-Line Thickness
| Autor: | Frank G. Shi, Jiun-Pyng You, Jielin Guo, Yu-Chou Shih, Roozbeh Sheikhi |
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| Rok vydání: | 2021 |
| Předmět: |
Materials science
General Chemical Engineering 02 engineering and technology bond-line thickness Article flip-chip LED 03 medical and health sciences Electrical resistance and conductance Chemical-mechanical planarization Nano Surface roughness heterogenous integration General Materials Science QD1-999 Nanoscopic scale 030304 developmental biology 0303 health sciences Interconnection business.industry nanoscale locking (NL) Contact resistance 021001 nanoscience & nanotechnology wet high temperature operating life (WHTOL) Electrical connection Chemistry Optoelectronics junction temperature 0210 nano-technology business electrical contact resistance |
| Zdroj: | Nanomaterials Nanomaterials, Vol 11, Iss 1901, p 1901 (2021) Volume 11 Issue 8 |
| ISSN: | 2079-4991 |
| DOI: | 10.3390/nano11081901 |
| Popis: | The potential of an innovation for establishing a simultaneous mechanical, thermal, and electrical connection between two metallic surfaces without requiring a prior time-consuming and expensive surface nanoscopic planarization and without requiring any intermediate conductive material has been explored. The method takes advantage of the intrinsic nanoscopic surface roughness on the interconnecting surfaces: the two surfaces are locked together for electrical interconnection and bonding with a conventional die bonder, and the connection is stabilized by a dielectric adhesive filled into nanoscale valleys on the interconnecting surfaces. This “nano-locking” (NL) method for chip interconnection and bonding is demonstrated by its application for the attachment of high-power GaN-based semiconductor dies to its device substrate. The bond-line thickness of the present NL method achieved is under 100 nm and several hundred times thinner than those achieved using mainstream bonding methods, resulting in a lower overall device thermal resistance and reduced electrical resistance, and thus an improved overall device performance and reliability. Different bond-line thickness strongly influences the overall contact area between the bonding surfaces, and in turn results in different contact resistance of the packaged devices enabled by the NL method and therefore changes the device performance and reliability. The present work opens a new direction for scalable, reliable, and simple nanoscale off-chip electrical interconnection and bonding for nano- and micro-electrical devices. Besides, the present method applies to the bonding of any surfaces with intrinsic or engineered surface nanoscopic structures as well. |
| Databáze: | OpenAIRE |
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