Congestion Prediction in FPGA Using Regression Based Learning Methods
| Autor: | Pingakshya Goswami, Dinesh Bhatia |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2021 |
| Předmět: |
TK7800-8360
Computer Networks and Communications Logic block Computer science Design flow Regression analysis machine learning Computer engineering Hardware and Architecture Control and Systems Engineering routing congestion Signal Processing Feature (machine learning) EDA prediction Electrical and Electronic Engineering Routing (electronic design automation) Physical design Electronics Field-programmable gate array Design closure |
| Zdroj: | Electronics, Vol 10, Iss 1995, p 1995 (2021) Electronics Volume 10 Issue 16 |
| ISSN: | 2079-9292 |
| Popis: | Design closure in general VLSI physical design flows and FPGA physical design flows is an important and time-consuming problem. Routing itself can consume as much as 70% of the total design time. Accurate congestion estimation during the early stages of the design flow can help alleviate last-minute routing-related surprises. This paper has described a methodology for a post-placement, machine learning-based routing congestion prediction model for FPGAs. Routing congestion is modeled as a regression problem. We have described the methods for generating training data, feature extractions, training, regression models, validation, and deployment approaches. We have tested our prediction model by using ISPD 2016 FPGA benchmarks. Our prediction method reports a very accurate localized congestion value in each channel around a configurable logic block (CLB). The localized congestion is predicted in both vertical and horizontal directions. We demonstrate the effectiveness of our model on completely unseen designs that are not initially part of the training data set. The generated results show significant improvement in terms of accuracy measured as mean absolute error and prediction time when compared against the latest state-of-the-art works. |
| Databáze: | OpenAIRE |
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