Modeling of DC - AC NBTI Stress - Recovery Time Kinetics in P-Channel Planar Bulk and FDSOI MOSFETs and FinFETs
| Autor: | Souvik Mahapatra, Nilesh Goel, Nilotpal Choudhury, A. Thirunavukkarasu, Narendra Parihar |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2020 |
| Předmět: |
Electron capture
NBTI Kinetics Silicon on insulator Thermionic emission 02 engineering and technology RD model 01 natural sciences Planar 0103 physical sciences ABDWT Electrical and Electronic Engineering TTOM 010302 applied physics Physics Stress recovery Negative-bias temperature instability Condensed matter physics BAT 021001 nanoscience & nanotechnology Electronic Optical and Magnetic Materials Threshold voltage lcsh:Electrical engineering. Electronics. Nuclear engineering 0210 nano-technology lcsh:TK1-9971 Biotechnology |
| Zdroj: | IEEE Journal of the Electron Devices Society, Vol 8, Pp 1281-1288 (2020) |
| ISSN: | 2168-6734 |
| Popis: | The physics-based BTI Analysis Tool (BAT) is used to model the time kinetics of threshold voltage shift ( $\Delta {\mathrm{ V}}_{\mathrm{ T}}$ ) during and after NBTI in p-channel planar bulk and FDSOI MOSFETs and SOI FinFETs. BAT uses uncorrelated contributions from the trap generation at the channel/gate insulator interface ( $\Delta {\mathrm{ V}}_{\mathrm{ IT}}$ ) and gate insulator bulk ( $\Delta {\mathrm{ V}}_{\mathrm{ OT}}$ ), and hole trapping in pre-existing gate insulator bulk traps ( $\Delta {\mathrm{ V}}_{\mathrm{ HT}}$ ). The $\Delta {\mathrm{ V}}_{\mathrm{ IT}}$ kinetics is simulated by the Reaction-Diffusion (RD) model. The empirical $\Delta {\mathrm{ V}}_{\mathrm{ HT}}$ model used earlier is now substituted by the Activated Barrier Double Well Thermionic (ABDWT) model. The ABDWT model is also used to verify the time constant of the electron capture induced fast $\Delta {\mathrm{ V}}_{\mathrm{ IT}}$ recovery. Empirical equations are used for $\Delta {\mathrm{ V}}_{\mathrm{ OT}}$ . The enhanced BAT modeling framework is validated using measured data from a wide range of experimental conditions and across different device architectures and gate insulator processes. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|