Implementation of an AFDX Interface with Zynq SoC Board in FPGA
Autor: | Guillermo De Scals, Pablo Corral, Miguel Aljaro, Alberto Rodriguez, Fernando Molina |
---|---|
Jazyk: | angličtina |
Rok vydání: | 2020 |
Předmět: |
business.industry
Computer science Event (computing) Avionics Full-Duplex Switched Ethernet Interface (computing) aerospace simulation aerospace electronics Scheduling (computing) Software Gate array Embedded system latency measurements lcsh:Electrical engineering. Electronics. Nuclear engineering Electrical and Electronic Engineering business Field-programmable gate array Protocol (object-oriented programming) afdx lcsh:TK1-9971 |
Zdroj: | Elektronika ir Elektrotechnika, Vol 26, Iss 5, Pp 11-15 (2020) |
ISSN: | 2029-5731 1392-1215 |
Popis: | This work is based on the Hardware development of the Transmission part for the communication inside the satellite. Our goal is move as much as possible of the software part into the Field-programmable gate array (FPGA) matrix due to the single event upsets (SEU). This project is part of the collaborative project called “Mission: NET@SPACE”. It was chosen by the European Commission under the Seventh Framework Program for Research (FP7) to develop an Avionics Full Duplex Switched Ethernet (AFDX) demonstrator based in FPGA. It has to be able to receive and transmit frames and enhance the robustness. The scheduling of the protocol should also be moved into the hardware, by still keeping a small footprint of the whole design. In this paper, we introduce the theory and used technologies, the project flow and development, including the decisions and milestones, to arrive at the end to the further possibilities and conclusions. |
Databáze: | OpenAIRE |
Externí odkaz: |