Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis
| Autor: | John Wickerson, Samuel Bayliss, George A. Constantinides, Junyi Liu |
|---|---|
| Přispěvatelé: | Engineering & Physical Science Research Council (EPSRC), Engineering & Physical Science Research Council (E, Royal Academy Of Engineering, Imagination Technologies Ltd |
| Rok vydání: | 2018 |
| Předmět: |
Technology
Computer Hardware & Architecture Computer science Pipeline (computing) Clock rate 02 engineering and technology Parallel computing polyhedral model Engineering high-level synthesis (HLS) Control theory High-level synthesis 0202 electrical engineering electronic engineering information engineering Overhead (computing) Electrical and Electronic Engineering Computer Science Hardware & Architecture Control logic Field-programmable gate array (FPGA) Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION 1006 Computer Hardware 020203 distributed computing Science & Technology Process (computing) Engineering Electrical & Electronic Computer Graphics and Computer-Aided Design loop pipelining 020202 computer hardware & architecture Loop (topology) 0906 Electrical and Electronic Engineering Computer Science reconfigurable computing Computer Science Interdisciplinary Applications Software |
| Zdroj: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 37:1802-1815 |
| ISSN: | 1937-4151 0278-0070 |
| DOI: | 10.1109/tcad.2017.2783363 |
| Popis: | Loop pipelining is one of the most important optimization methods in high-level synthesis (HLS) for increasing loop parallelism. There has been considerable work on improving loop pipelining, which mainly focuses on optimizing static operation scheduling and parallel memory accesses. Nonetheless, when loops contain complex memory dependencies, current techniques cannot generate high performance pipelines. In this paper, we extend the capability of loop pipelining in HLS to handle loops with uncertain dependencies (i.e., parameterized by an undetermined variable) and/or nonuniform dependencies (i.e., varying between loop iterations). Our optimization allows a pipeline to be statically scheduled without the aforementioned memory dependencies, but an associated controller will change the execution speed of loop iterations at runtime. This allows the augmented pipeline to process each loop iteration as fast as possible without violating memory dependencies. We use a parametric polyhedral analysis to generate the control logic for when to safely run all loop iterations in the pipeline and when to break the pipeline execution to resolve memory conflicts. Our techniques have been prototyped in an automated source-to-source code transformation framework, with Xilinx Vivado HLS, a leading HLS tool, as the RTL generation backend. Over a suite of benchmarks, experiments show that our optimization can implement optimized pipelines at almost the same clock speed as without our transformations, running approximately 3.7– $10{\times }$ faster, with a reasonable resource overhead. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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