Test circuits for fast and reliable assessment of CDM robustness of I/O stages
| Autor: | A. Konrad, Wolfgang Stadler, Heinrich Wolf, M. Frank, N. Qu, Antonio Andreini, H. Gieser, M. Etherton, Kai Esmark, Dionyz Pogany, M. Graf, E. Morena, D. Nuernbergk, J. Willemen, Erich Gornik, M.I. Natarajan, Roberto Stella, Guido Groeseneken, S. Mettler, W. Soppa, Koen Reynders, C. Foss, Wolfgang Wilkening, V. De Heyn, Martin Litzenberger, Mahmud Zubeidat |
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| Přispěvatelé: | Publica |
| Předmět: |
Engineering
Robustness (computer science) business.industry Electronic engineering Electrical and Electronic Engineering Device simulation Safety Risk Reliability and Quality Condensed Matter Physics business Atomic and Molecular Physics and Optics Surfaces Coatings and Films Electronic Optical and Magnetic Materials Electronic circuit |
| Zdroj: | Scopus-Elsevier |
| Popis: | CDM hardening during the development of technology, devices, libraries and finally products differs significantly from the process well-established for HBM. This paper introduces a method on the basis of specialized CDM test structures including protection elements and sensitive monitor elements. These test structures mimic typical CDM-sensitive circuits found by physical failure analysis over the years. Manufactured in five different technologies, structures were assembled in both a regular package and a new package emulator. CDM stress tests, very-fast TLP tests, transient interferometric mapping, device simulation, and failure analysis lead to new insights in the complex interdependencies during CDM and underline the need of CDM-specific test structures. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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