Dedicated wavelet QRS complex detection for FPGA implementation
| Autor: | Bo Zhang, Loic Sieler, Benoît Bolmont, Guy Bourhis, Yann Morère |
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| Přispěvatelé: | Institut für Informatik (LRR-TUM), Technische Universität Munchen - Université Technique de Munich [Munich, Allemagne] (TUM), Laboratoire de Conception, Optimisation et Modélisation des Systèmes (LCOMS), Université de Lorraine (UL) |
| Jazyk: | angličtina |
| Rok vydání: | 2017 |
| Předmět: |
Floating point
Computer science business.industry 020208 electrical & electronic engineering SIGNAL (programming language) Wavelet transform 02 engineering and technology Chip [SPI.AUTO]Engineering Sciences [physics]/Automatic 03 medical and health sciences 0302 clinical medicine Wavelet VHDL 0202 electrical engineering electronic engineering information engineering 030212 general & internal medicine business Field-programmable gate array computer [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing Computer hardware ComputingMilieux_MISCELLANEOUS Integer (computer science) computer.programming_language |
| Zdroj: | 2017 International Conference on Advanced Technologies for Signal and Image Processing (ATSIP) 2017 International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), May 2017, Fez, France. pp.1-6, ⟨10.1109/ATSIP.2017.8075543⟩ ATSIP |
| Popis: | The QRS complex is the most significant segment in the Electrocardiography (ECG) signal. By detecting its position, we can learn the physiological informations of the subjects, e.g. heart rate. In this paper, we propose a FPGA architecture for QRS complex detection. The detection algorithm is based on Integer Haar Transform (IHT). Due to its integer nature, the IHT avoids the floating point calculations and thus can be easily implemented in FPGA. The FPGA Cyclone EP3C5F256C6 is used as the target chip and all the components of the system are implemented in VHSIC Hardware Description Language (VHDL). The testing results show that the proposed FPGA architecture can achieve an efficient detection performance where the total detection accuracy exceeds 98%. Meanwhile, the FPGA implementation shows good design efficiency in the term of silicon consumption. Only 8% silicon resources of the target chip are occupied. The proposed architecture will be adopted as a core unit to make a FPGA system for stress recognition given the heterogeneous data. |
| Databáze: | OpenAIRE |
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