A Review Report on Multi-Voltage Rule Check and Formal Verification of ASIC Design

Autor: Mythili, M., Badiger, Sujata D, Singh, Jayati, Venkata Rangam Totakura
Jazyk: angličtina
Rok vydání: 2020
Předmět:
DOI: 10.5281/zenodo.3890999
Popis: In order to decrease the power dissipation in ASIC design, Multi-voltage design techniques such as Power gating, Clock gating, Power down mode, Multi-threshold, etc. are employed. To help designers verify the correct implementation of these low power design techniques, Multi-voltage Rule Check is used. The implementation of different Multi-voltage design elements such as Isolation Cell, Level Shifter Cell, Retention Cell and power aware design is explained using Unified power format (UPF). And in the design process from Register-transfer level (RTL) to Graphic Database System (GDSII) various changes are made to the netlist to make it easily testable, to satisfy the timing constraints, to optimally place and route the design. These processes introduce variations in the netlist, which must be checked to make sure that its functionality has not changed. So Formal Verification is performed to confirm that Golden netlist (Reference) and revised netlist are equivalent at different phases, example Synthesis, Design for Testability (DFT), Place and route. This paper discusses the different mathematical algorithms underlying formal Verification such as Binary decision diagram and Satisfiability solvers. It provides a detailed review of both formal verification and multi-voltage rule check.
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Databáze: OpenAIRE
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