Design of Reconfigurable Logic Controllers from Petri Net-based specifications
| Autor: | Marek Wegrzyn, Marian Adamski |
|---|---|
| Rok vydání: | 2009 |
| Předmět: |
Rapid prototyping
business.industry Computer science Logic family Petri net Programmable logic device Logic synthesis Embedded system VHDL business Field-programmable gate array Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION computer Hardware_LOGICDESIGN computer.programming_language Register-transfer level Logic optimization |
| Zdroj: | Scopus-Elsevier |
| ISSN: | 1474-6670 |
| DOI: | 10.3182/20091006-3-es-4010.00036 |
| Popis: | The paper promotes to construct a synthesizable VHDL model from a graphical representation of Petri Net. The VHDL code provides a clear semantics of graphically designed reconfigurable logic controller and serves as reference model for eventual further optimization efforts. It is considered that automatically generated array structure of logic controller is optimized for synthesis by professional tools. The most useful aspect for presented purposes is the ability to execute a VHDL behavioral specification closely related with array-based implementation. Even if the final implementation is not optimized during the logic synthesis process, it is compact, easy to modify and efficient. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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