A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells
| Autor: | Akira Matsuzawa, Noriaki Takeda, Shiro Dosho, Masao Takayama, Masaya Miyahara |
|---|---|
| Rok vydání: | 2013 |
| Předmět: |
business.industry
Computer science Amplifier Electrical engineering Successive approximation ADC Signal edge Chip Signal Electronic Optical and Magnetic Materials Time-to-digital converter Effective number of bits Analog signal Hardware_INTEGRATEDCIRCUITS Electronic engineering Time domain Electrical and Electronic Engineering business Phase modulation |
| Zdroj: | A-SSCC |
| ISSN: | 1745-1353 0916-8524 |
| Popis: | In this paper, we describe a new method to deal with analog signal in time domain. The method converts voltage signal to time-interleaved phase modulation signal of clock edge. After being amplified by a new time amplifier(TA), phases of the signal are converted to digital codes by successive approximation time-to-digital converter(SA-TDC). The test chip includes 8 interleaved 4bit SA-TDCs with short latency. The chip operates up to 4.4GHz. The measured ENOB is 3.51bit and FOM is 0.49pJ/conv. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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