A configurable CMOS multiplier/divider for analog VLSI
| Autor: | R. Khan, Mohammed Ismail, R. Brannen, Nabil I. Khachab, Shigetaka Takagi, Nobuo Fujii, O. Aaserud |
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| Rok vydání: | 2005 |
| Předmět: |
Very-large-scale integration
Computer science business.industry Analog computer Bandwidth (signal processing) Transistor Electrical engineering Impedance matching Hardware_PERFORMANCEANDRELIABILITY Analog signal processing Current divider Analog multiplier law.invention Frequency divider Parasitic capacitance CMOS Hardware_GENERAL law MOSFET Hardware_INTEGRATEDCIRCUITS Operational amplifier Electronic engineering Multiplier (economics) business Hardware_LOGICDESIGN |
| Zdroj: | ISCAS |
| Popis: | The design of a simple CMOS operational-amplifier-based multiplier/divider is presented. The 2 operational amplifier and 6 MOSFET transistor circuit simultaneously achieves four-quadrant multiplication and division. Applications of the new circuit in analog signal processing are discussed. The multiplier/divider circuit is insensitive to MOS intrinsic parasitic capacitances. It is sensitive to operational amplifier finite unity-gain bandwidth. This sensitivity may be mitigated using the configurability property of the circuit. Experimental results are provided to support some of the theoretical claims. > |
| Databáze: | OpenAIRE |
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