Sharp switching, hysteresis-free characteristics of Z 2 -FET for fast logic applications
| Autor: | Kyung Hwa Lee, S. Sato, Pascal Fonteneau, H. El Dirani, Sorin Cristoloveanu, Maryline Bawedin |
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| Přispěvatelé: | STMicroelectronics [Crolles] (ST-CROLLES), STMicroelectronics [Grenoble] (ST-GRENOBLE), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]) |
| Jazyk: | angličtina |
| Rok vydání: | 2018 |
| Předmět: |
Silicon on insulator
Z2-FET 02 engineering and technology Integrated circuit Hardware_PERFORMANCEANDRELIABILITY 01 natural sciences 7. Clean energy law.invention law 0103 physical sciences Hardware_INTEGRATEDCIRCUITS [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Fully Depleted SOI (FDSOI) 010302 applied physics Physics business.industry 021001 nanoscience & nanotechnology Logic Switch Subthreshold slope Anode Impact ionization Hysteresis Dual Ground Planes Logic gate Optoelectronics 0210 nano-technology business Dram band-modulation Hardware_LOGICDESIGN Sharp Switch |
| Zdroj: | 2018 ESSDERC Proceedings 2018 ESSDERC-48th European Solid-State Device Research Conference (ESSDERC) 2018 ESSDERC-48th European Solid-State Device Research Conference (ESSDERC), Sep 2018, Dresden, Germany. pp.74-77, ⟨10.1109/ESSDERC.2018.8486915⟩ ESSDERC |
| Popis: | session A4L-F: Emerging Devices and Applications; International audience; A logic switch for integrated circuits is demonstrated experimentally in advanced FDSOI (Fully Depleted SOI). The Z 2 -FET (Zero Impact Ionization and Zero Subthreshold Slope FET) is a band-modulation device that shows remarkable performance in terms of ON/OFF current ratio and sharp switch (~ 1 mV/decade). The Z 2 -FET capability for ESD protection and capacitorless DRAM has already been documented. However, the presence of an inherent hysteresis effect has inhibited so far fast logic applications. A new generation of Z 2 -FETs with single or dual ground-plane has been fabricated with Ultra-Thin Body and Buried Oxide (UTBB) SOI technology. We demonstrate that fast pulses on the gate result in hysteresis-free switching: the device turns ON and OFF at same gate bias. Systematic measurements reveal the key roles of the device parameters and bias on the speed of operation. |
| Databáze: | OpenAIRE |
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