Stress Evaluations of Silicon Nitride Chips Bonded onto Copper Substrates via SAC Soldering, AuSn Soldering, and Copper Sintering
| Autor: | Fosca Conti, Gordon Elger, Roland Seitz, Sri Krishna Bhogaraju, E Liu, Christoph Lenz |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
Silicon nitride
Tin alloys Materials science Packaging technologies Copper interconnect Chip scale packages chemistry.chemical_element Sintering 02 engineering and technology Lead-free solders 01 natural sciences Power electronic modules Nitrides Stress (mechanics) Electric insulation chemistry.chemical_compound Integrated circuit interconnects Gold metallography 0103 physical sciences Stress relaxation Architectural acoustics Tin metallography Composite material 010302 applied physics Coefficients of thermal expansions Substrates Architectural acoustics Chip scale packages Electric insulation Gold alloys Gold metallography Integrated circuit interconnects Lead-free solders Mechanical stability Nitrides Silicon nitride Sintering Soldering Stress relaxation Substrates Thermal expansion Tin alloys Tin metallography Coefficients of thermal expansions Copper interconnects Micro Raman Spectroscopy Multi-layer architectures Multi-phase morphology Packaging technologies Power electronic modules Thermomechanical stability Soldering 021001 nanoscience & nanotechnology Copper Mechanical stability Thermomechanical stability chemistry Multi-layer architectures Heat spreader Thermal expansion Micro Raman Spectroscopy 0210 nano-technology Gold alloys Copper interconnects Multi-phase morphology |
| Zdroj: | 2020 26th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC). |
| DOI: | 10.1109/therminic49743.2020.9420523 |
| Popis: | Power electronic modules require multi-layer architectures, where the layers provide dedicated functions, e.g. active semiconductor chip, electric conduction layer, heat spreader, insulation layer. All the layers have different material properties, like coefficients of thermal expansion. Due to their mismatch, local stresses are induced, which can cause electronic failure in packaging technologies. In this regard, new materials need to be developed, which provide high thermo-mechanical stability. In addition, innovative interconnect processes are required, which minimize the formation of stresses. Silicon nitride (Si 3 N 4 ) chips with polycrystalline and multi-phase morphology are investigated. The chips are sintered to copper substrates using a Cu(II)formate/polyethylene glycol sinter paste. In reference to the sintered copper interconnect, SAC and AuSn solder interconnects are also analysed. The final assemblies are studied using micro-Raman spectroscopy. The frequency changes of the E 1g vibrational mode at ca. 860 cm−1 are observed to detect intrinsic tensile and compressive local stresses. Stress values between 640 and 400 MPa are detected in the Si 3 N 4/ AuSn/Cu assemblies, while in all other assemblies stress relaxation appears very efficient. |
| Databáze: | OpenAIRE |
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