CNTFET design of a multiple-port ternary register file
| Autor: | Lobna A. Said, Ihsen Alouani, Ahmed G. Radwan, Amr Mohammaden, Mohammed E. Fouda |
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| Přispěvatelé: | Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA), Université catholique de Lille (UCL)-Université catholique de Lille (UCL), COMmunications NUMériques - IEMN (COMNUM - IEMN), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Université catholique de Lille (UCL)-Université catholique de Lille (UCL)-Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA) |
| Rok vydání: | 2021 |
| Předmět: |
Computer science
Dynamic Register file Binary number 02 engineering and technology Ternary computer CNTFET 01 natural sciences law.invention [SPI]Engineering Sciences [physics] law 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Electronic engineering Flip flop Hardware_ARITHMETICANDLOGICSTRUCTURES Ternary logic gates 010302 applied physics Hardware_MEMORYSTRUCTURES 020208 electrical & electronic engineering General Engineering Information processing CNTEFT Carbon nanotube field-effect transistor Latch D-latch CMOS Ternary operation Realization (systems) Hardware_LOGICDESIGN |
| Zdroj: | Microelectronics Journal Microelectronics Journal, 2021, 113, pp.105076. ⟨10.1016/j.mejo.2021.105076⟩ |
| ISSN: | 0026-2692 |
| DOI: | 10.1016/j.mejo.2021.105076 |
| Popis: | International audience; Ternary number system offers higher information processing within the same number of digits when compared to binary systems. Such advantage motivated the development of ternary processing units especially with CNTFET which offers better power and delay results compared to CMOS-based realization. In this paper, we propose a variety of circuit realizations for the ternary memory elements that are needed in any processor including ternary D-latch, and ternary D-flip-flop. These basic building blocks are then used to design a ternary register file with multiple read and write ports. This paper is an attempt to investigate the performance aspects of using ternary RF to open the gate of more contributions and research in the direction of full ternary computer architecture. The proposed designs have been compared in terms of power, area, and latency at different supply voltages and operating temperatures. |
| Databáze: | OpenAIRE |
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