Understanding the Impact of Annealing on Interface and Border Traps in the Cr/HfO2/Al2O3/MoS2 System
Autor: | Andrea Padovani, Robert M. Wallace, Paul K. Hurley, Ava Khosravi, Luca Larcher, Pavel Bolshakov, Chadwin D. Young, Peng Zhao, Christopher L. Hinkle |
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Jazyk: | angličtina |
Rok vydání: | 2019 |
Předmět: |
Materials science
Annealing (metallurgy) business.industry Gate dielectric Transistor Electronic Optical and Magnetic Materials law.invention Capacitance-voltage (C-V) Border traps law Molybdenum disulfide (MoS2) Al2O3 Materials Chemistry Electrochemistry Optoelectronics business High-k dielectrics Interface traps |
Popis: | Top-gated, few-layer MoS2 transistors with HfO2 (6 nm)/Al2O3 (3 nm) gate dielectric stacks are fabricated and electrically characterized by capacitance–voltage (C–V) measurements to study electrically active traps (Dit) in the vicinity of the Al2O3/MoS2 interface. Devices with low Dit and high Dit are both observed in C–V characterization, and the impact of H2/N2 forming gas annealing at 300 and 400 °C on the Dit density and distribution is studied. A 300 °C anneal is able to reduce the Dit significantly, while the 400 °C anneal increases defects in the gate stack. Simulation with modeled defects suggests a sizable decrease in Dit, half the amount of positive fixed charge in the dielectric, and slightly increased unintentional doping in MoS2 after a 300 °C anneal. In the as-fabricated devices displaying high Dit levels, the energy distribution of the Dit located at the Al2O3/MoS2 interface is continuous from the conduction band edge of MoS2 down to 0.13–0.35 eV below the conduction band edge. A plausible Dit origin in our experiments could come from the unexpected oxygen atoms that fill the sulfur vacancies during the UV–O3 functionalization treatment. The border trap concentration in Al2O3 is the same, both before and after the anneal, suggesting a different origin of the border traps, possibly due to the low-temperature atomic-layer-deposited process. |
Databáze: | OpenAIRE |
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