Reversible Computing with Fast, Fully Static, Fully Adiabatic CMOS
| Autor: | Brian D. Tierney, Robert W. Brocato, Michael P. Frank, Nancy A. Missert, Alexander H. Hsia |
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| Rok vydání: | 2020 |
| Předmět: |
FOS: Computer and information sciences
Digital electronics Sequential logic business.industry Computer science Logic family Computer Science - Emerging Technologies Hardware_PERFORMANCEANDRELIABILITY Computer Science::Hardware Architecture Emerging Technologies (cs.ET) Logic synthesis CMOS Low-power electronics Hardware Architecture (cs.AR) Hardware_INTEGRATEDCIRCUITS Electronic engineering Reversible computing Computer Science - Hardware Architecture Adiabatic process business Hardware_LOGICDESIGN |
| Zdroj: | ICRC |
| DOI: | 10.1109/icrc2020.2020.00014 |
| Popis: | To advance the energy efficiency of general digital computing far beyond the thermodynamic limits that apply to conventional digital circuits will require utilizing the principles of reversible computing. It has been known since the early 1990s that reversible computing based on adiabatic switching is possible in CMOS, although almost all of the "adiabatic" CMOS logic families in the literature are not actually fully adiabatic, which limits their achievable energy savings. The first CMOS logic style that achieved truly, fully adiabatic operation if leakage was negligible (CRL) is not fully static, which leads to a number of practical engineering difficulties in the presence of certain nonidealities. Later, "static" adiabatic logic families were described, but they were not actually fully adiabatic, or fully static, and were much slower. In this paper, we describe a new logic family, Static 2-Level Adiabatic Logic (S2LAL), which is, to our knowledge, the first CMOS logic family that is both fully static, and truly, fully adiabatic (modulo leakage). In addition, S2LAL is, we think, the fastest possible such family (among fully pipelined sequential circuits), having a latency per logic stage of one "tick" (transition time), and a minimum clock period (initiation interval) of 8 ticks. S2LAL requires 8 phases of a trapezoidal power-clock waveform (plus constant power and ground references) to be supplied. We argue that, if implemented in a suitable fabrication process designed to aggressively minimize leakage, S2LAL should be capable of demonstrating a greater level of energy efficiency than any other semiconductor-based digital logic family known today. Comment: 8 pages, 9 figures, submitted to the IEEE International Conference on Rebooting Computing (ICRC 2020) |
| Databáze: | OpenAIRE |
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