Ultralow Latency HIL Platform for Rapid Development of Complex Power Electronics Systems
| Autor: | Ivan Celanovic, Stevan Grabic, Dusan Majstorovic, Marko Vekic, Vladimir Katic, Nikola Celanovic |
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| Rok vydání: | 2012 |
| Předmět: | |
| Zdroj: | IEEE Transactions on Power Electronics. 27:4436-4444 |
| ISSN: | 1941-0107 0885-8993 |
| DOI: | 10.1109/tpel.2012.2190097 |
| Popis: | Prototyping and verification of complex power electronics (PE) systems and control algorithms is a laborious and time-consuming process. Even when a low-power hardware model is assembled, it enables only a limited insight into the large number of operating points; changes in system parameters regularly demand hardware modifications and always there is the risk of hardware damage. The ultralow-latency Hardware-In-the-Loop (HIL) platform proposed in this paper combines the flexibility, accuracy, and ease of use of state-of-the-art-simulation packages, with the response speed of small power-hardware models. In this way, PE systems-optimization, code-development, and laboratory-testing can be combined into one step, which dramatically accelerates the pace of product prototyping. Low-power hardware-models also suffer from nonscalability, because some parameters such as electrical machine inertia cannot be properly scaled. However, HIL enables control prototyping that covers all operational conditions. In order to demonstrate HIL-based rapid development, the verification of an active damping algorithm for a permanent magnet synchronous generator (PMSG) cascade is performed. Two goals are set in this paper: to verify the developed HIL platform by means of comparison with a low-power hardware setup and then to emulate the real, high-power system in order to test the active damping algorithm. |
| Databáze: | OpenAIRE |
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