Performance-driven Wire Sizing for Analog Integrated Circuits

Autor:	Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind Sharma, Sachin Sapatnekar, Ramesh Harjani, Jiang Hu
Rok vydání:	2022
Předmět:	Electrical and Electronic Engineering Computer Graphics and Computer-Aided Design Computer Science Applications
Zdroj:	ACM Transactions on Design Automation of Electronic Systems. 28:1-23
ISSN:	1557-7309 1084-4309
DOI:	10.1145/3559542
Popis:	Analog IC performance has a strong dependence on interconnect RC parasitics, which are significantly affected by wire sizes in recent technologies, where minimum-width wires have high resistance. However, performance-driven wire sizing for analog ICs has received very little research attention. In order to fill this void, we develop several techniques to facilitate an end-to-end automatic wire sizing approach. They include a circuit performance model based on customized graph neural network (GNN) and two optimization techniques: one using Bayesian optimization accelerated by the GNN model, and the other based on TensorFlow training. Experimental results show that our technique can achieve 11% circuit performance improvement or 8.7× speedup compared to a conventional Bayesian optimization method.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::ff02a500c28433752ff1f04c7782a9f4 https://doi.org/10.1145/3559542 Zobrazit plný text záznamu