A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth

Autor:	Keum-Yong Kim, Ejaz Haq, Kye-Hyun Kyung, Kinam Kim, Bok-Moon Kang, Moon-Hae Son, Chang-Hyun Kim, Hyung-Kyu Lim, Soo-In Cho, K. H. Lee, Jai-Hoon Sim, Sang-Bo Lee, Jae-Gwan Park, Jong-Woo Park, Jung-Hwa Lee, Seung-Moon Yoo, Jei-Hwan Yoo, Joungho Kim, Jinman Han, Byung-sik Moon, Kang-yoon Lee, Kyu-Chan Lee
Rok vydání:	1996
Předmět:	Random access memory business.industry Computer science Bandwidth (signal processing) Electrical engineering Chip CMOS Memory architecture Electronic engineering Redundancy (engineering) Electrical and Electronic Engineering business Dram Access time Electronic circuit
Zdroj:	IEEE Journal of Solid-State Circuits. 31:1635-1644
ISSN:	1558-173X 0018-9200
Popis:	This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V/sub cc/=2.0 V and 25/spl deg/C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an extended small swing read operation and a single I/O line driving write scheme to reduce power consumption; (3) a self-strobing I/O schemes to achieve high bandwidth with low power dissipation; and (4) a block redundancy scheme with increased flexibility. The nonstitched chip with an area of 652 mm/sup 2/ has been fabricated using 0.16 /spl mu/m four-poly, four-metal CMOS process technology.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::fe8f35bf377499dd5f1a434eea274fb8 https://doi.org/10.1109/jssc.1996.542308 Zobrazit plný text záznamu