Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors

Autor:	Charles L. Wang, Tin Tin Wee, Cooper Jeffrey, Sanjeev Maheshwari, Dennis M. Fischette, Michael M. Oshima, Gerry R. Talbot, Sanjeev Aggarwal, Chad O. Lackey, Alvin Leng Sun Loke, Harishkumar S. Kedarnath, Emerson S. Fang, Bruce A. Doyle
Rok vydání:	2011
Předmět:	Phase-locked loop Engineering CMOS business.industry Embedded system HyperTransport Integrated circuit design Integrated circuit packaging Transceiver business Computer hardware Jitter Electronic circuit
Zdroj:	A-SSCC
DOI:	10.1109/asscc.2011.6123620
Popis:	We present an 8.0-Gb/s HyperTransport™ technology I/O built in a 32-nm SOI-CMOS processor for high-performance servers. Based on a 45-nm design that caps at 6.4 Gb/s, the 32-nm transceiver achieves up to 8.0 Gb/s over long-reach board channels. Key enhancements include a high-bandwidth (>200 MHz) PLL to attenuate high-frequency jitter in the received forwarded clock and redesigned power-hungry circuits to operate at 8.0 Gb/s within the existing 45-nm package thermal limit.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::fe19547e68c15e6bce12dbd218bf64c6 https://doi.org/10.1109/asscc.2011.6123620 Zobrazit plný text záznamu