VLSI Implementation of Burrows Wheeler Transform for Memory Reduced Distributed Arithmetic Architectures
| Autor: | C. Shiny, A S Remya Ajai, Lintu Rajan |
|---|---|
| Rok vydání: | 2012 |
| Předmět: |
Discrete wavelet transform
Very-large-scale integration Burrows–Wheeler transform business.industry Computer science Data_CODINGANDINFORMATIONTHEORY computer.file_format Parallel computing Wavelet JPEG 2000 Field-programmable gate array business computer Digital signal processing Coding (social sciences) |
| Zdroj: | Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering ISBN: 9783642356148 |
| DOI: | 10.1007/978-3-642-35615-5_36 |
| Popis: | Multiply and accumulate function is the important part of digital signal processing algorithms. This can be implemented more effectively with distributed arithmetic (DA) architecture [1]. These architectures make extensive use of look-up tables, which make them ideal for implementing digital signal processing functions on Xilinx FPGAs. An emerging arithmetic-intensive digital signal processing algorithm is the discrete wavelet transform (DWT) which have proven to be extremely useful for image and video coding applications like MPEG-4 and JPEG 2000[2]. But the limitation of this architecture is that the size of look-up tables get increased exponentially as the constant coefficients of wavelet used for these applications increases. In this paper, we proposed a novel methodology to implement the Burrows wheeler transform (BWT) [3] block in FPGA for achieving memory reduced DA. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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