Configurable Input–Output Power Pad for Wafer-Scale Microelectronic Systems
| Autor: | Walder Andre, Olivier Valorge, Yves Blaquiere, Mohamad Sawan, Nicolas Laflamme-Mayer |
|---|---|
| Rok vydání: | 2013 |
| Předmět: |
Input/output
Engineering Wafer-scale integration business.industry Transistor Electrical engineering Topology (electrical circuits) Hardware_PERFORMANCEANDRELIABILITY Voltage regulator law.invention CMOS Hardware and Architecture law Load regulation Hardware_INTEGRATEDCIRCUITS Electrical and Electronic Engineering business Software Voltage |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21:2024-2033 |
| ISSN: | 1557-9999 1063-8210 |
| DOI: | 10.1109/tvlsi.2012.2223247 |
| Popis: | We describe, in this paper, a new digital input-output power configurable PAD (CPAD) for a wafer-scale-based rapid prototyping platform for electronic systems. This wafer-scale platform includes a reconfigurable wafer-scale circuit that can interconnect any digital components manually deposited on its active alignment-insensitive surface. The whole platform is powered using a massive grid of embedded voltage regulators. Power is fed from the bottom side of the wafer using through silicon vias. The CPAD can be configured to provide CMOS standard voltages of 1.0, 1.5, 1.8, 2.0, 2.5, and 3.3 V using a single 3.3 V power supply. The digital I/O includes transistors sharing and is embedded within the regulation circuit by combining it with a turbo mode that insures high-speed operation. Fast load regulation is achieved with a 5.5-ns response time to a current step load for a maximum current of 110 mA per CPAD. The proposed circuit architecture benefits from a hierarchical arborescence topology where one master stage drives 16 CPADs with a very small quiescent current of 366 nA. The CPAD circuit and the master stage occupy a small area of 0.00847 and 0.00726 mm2, respectively, in CMOS 0.18-μm technology. |
| Databáze: | OpenAIRE |
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