CMOS 12 bits 50kS/s micropower SAR and dual-slope hybrid ADC
| Autor: | Vijay Srinivasan, Jack Wills, John Choma, Xiang Fang, John J. Granacki, Jeff LaCoss |
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| Rok vydání: | 2009 |
| Předmět: |
Engineering
business.industry Electrical engineering Successive approximation ADC Micropower Hardware_PERFORMANCEANDRELIABILITY Effective number of bits CMOS Integrator Low-power electronics Hardware_INTEGRATEDCIRCUITS Electronic engineering System on a chip Hardware_ARITHMETICANDLOGICSTRUCTURES business Low voltage |
| Zdroj: | 2009 52nd IEEE International Midwest Symposium on Circuits and Systems. |
| DOI: | 10.1109/mwscas.2009.5236122 |
| Popis: | In this paper a 12 bits 50kS/s micropower hybrid ADC is proposed for biomimetic microelectronic systems using 0.18um CMOS process. The hybrid ADC combines SAR and dual-slope architectures to achieve 12 bits, power consumption 60uW, and small silicon die size. This hybrid ADC shows very good figure-of-merits (FOM) on both power consumption and silicon die size compared with conventional low power SAR ADC. A fully differential GmC integrator is proposed for the dual-slope operation with low voltage discrete-time CMFB. |
| Databáze: | OpenAIRE |
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