| Autor: |
Shyue-Shyh Lin, H.C. Tseng, S. Pan, Keh-Jeng Chang, Akis Dagonis, Kelvin Doong |
| Rok vydání: |
2009 |
| Předmět: |
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| Zdroj: |
2009 IEEE International Conference on Microelectronic Test Structures. |
| Popis: |
To maximize the design efficiency of the test chip area and maintain the high accuracy measurement requirement of resistors and capacitors, a 4K-cells resistive and charge-base capacitive test structure array is designed for CMOS logic process development, monitor and model. The test chip utilizes 4-terminal (one of 4 is strongly grounded) Kelvin force/sense measurement for resistive-type and charge-base capacitance measurement (CBCM) for capacitive-type test structures. With the aid of memory-addressing design scheme, any one of the device-under-test in an array can be randomly or sequentially selected for testing with all of them sharing a common probe pad group. To accelerate the testing speed, the address control signals of 8 test structure array are connected in parallel for synchronized parallel testing. A 32×16×8 test structure array has been implemented by utilizing a state-of-the-art logic process to demonstrate design feasibility. The results confirm the excellence of this architecture in measurement with 0.1fF for capacitive and 0.1 ohm for resistive systematic errors, and 7 times testing speed improvement. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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