An architecture for MPEG-4 binary shape decoder

Autor:	J. Thinakaran, Nam Ling, Duan-Juat Ho
Rok vydání:	2002
Předmět:	Speedup Computer science business.industry Hardware description language Binary number Data_CODINGANDINFORMATIONTHEORY computer.file_format Soft-decision decoder VHDL MPEG-4 Electronic engineering business computer Decoding methods Computer hardware computer.programming_language Shift register
Zdroj:	ISCAS
DOI:	10.1109/iscas.2000.856363
Popis:	An architecture for MPEG-4 binary shape decoder is presented. Our novel techniques include a look-ahead unit to speed up the probability generation process, the usage of synchronous ROM for reduced power consumption, and the use of simple shift registers instead of large barrel shifters to reduce the area of the decoder. The decoder architecture is designed using VHDL. The decoder is able to decode up to 100 Mbits/s and can be used to achieve Main Profile at Level Three performance requirement.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::fbffa77a1c00732ecaa978ee3f7a0d7e https://doi.org/10.1109/iscas.2000.856363 Zobrazit plný text záznamu