Foveros: 3D Integration and the use of Face-to-Face Chip Stacking for Logic Devices

Autor:	H. Ma, G.-S. Kim, Daniel Pantuso, L. Aryasomayajula, D. Borst, R. Criss, S. Amin, P. Sinha, K. C. Kolluru, Patrick N. Stover, D. Ingerly, David Jones, K. Cheemalapati, C. S. Cook, K. Enamul, A. M. Pillai, Z. Zell, A. Sairam, A. Kandas, Prabhanshu Shekhar, Gomes Wilfred, Aparna Telang, C.F. Petersburg, M. Phen-givoni, Ajay Balankutty, A. Chandra
Rok vydání:	2019
Předmět:	Silicon Computer science 020209 energy 020208 electrical & electronic engineering Stacking chemistry.chemical_element 02 engineering and technology Chip stacking Die (integrated circuit) Connection (mathematics) chemistry 0202 electrical engineering electronic engineering information engineering Key (cryptography) Electronic engineering Low resistance
Zdroj:	2019 IEEE International Electron Devices Meeting (IEDM).
Popis:	This paper presents the key silicon features of Intel’s 3D stacking technology, Foveros, as it is used to enable logic-on-logic die stacking. A robust face-to-face die connection is enabled with a high yielding, robust microbump connection. Additionally, we describe the low resistance TSVs used for connection to the package along with their electrical properties.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::fbeabd66e2f12ee2392406487a1e4d72 https://doi.org/10.1109/iedm19573.2019.8993637 Zobrazit plný text záznamu