The impact of RTN on performance fluctuation in CMOS logic circuits
| Autor: | Kazutoshi Kobayashi, Shinichi Nishizawa, Hiroki Sunagawa, Hidetoshi Onodera, Kyosuke Ito, Takashi Matsumoto |
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| Rok vydání: | 2011 |
| Předmět: |
Sequential logic
business.industry Computer science Matrix Array Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Noise (electronics) Time–frequency analysis Frequency conversion Logic gate Hardware_INTEGRATEDCIRCUITS Electronic engineering Cmos logic circuits business Low voltage Hardware_LOGICDESIGN |
| Zdroj: | 2011 International Reliability Physics Symposium. |
| Popis: | In this paper, the impact of Random Telegraph Noise (RTN) on CMOS logic circuits observed in a Circuit Matrix Array is reported. We discuss the behavior of RTN under circuit operation, and reveal that the impact of RTN, which is much smaller than that of within-die variation in a 65nm process, can have a severe effect on the performance of a sequential logic gate under low voltage operation. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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