An Adaptive Loop Gain Tracking Digital PLL Using Spectrum-Balancing Technique
Autor: | Guan-Yu Su, Zhi-Heng Kang, Shen-Iuan Liu |
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Rok vydání: | 2021 |
Předmět: |
Loop (topology)
Phase-locked loop Control theory Computer science 020208 electrical & electronic engineering DPLL algorithm Detector Phase noise 0202 electrical engineering electronic engineering information engineering 02 engineering and technology 020202 computer hardware & architecture Loop gain Jitter |
Zdroj: | VLSI-DAT |
DOI: | 10.1109/vlsi-dat52063.2021.9427319 |
Popis: | A digital phase-locked loop (DPLL) using the proposed adaptive loop gain controller (ALGC) is presented. The ALGC uses a spectrum-balancing technique to detect the difference of the high-frequency and the low-frequency powers of the bang-bang phase-frequency detector output. Then, the loop gain of the DPLL is adjusted to minimize the output root-mean-square (RMS) jitter. This DPLL is fabricated in 40-nm CMOS process and its active area is 0.016mm2. Operating at a frequency of 3.2 GHz, the power consumption of the DPLL is 1.5mW from a 1V supply voltage. |
Databáze: | OpenAIRE |
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