| Autor: |
Mahbub Rashed, Joerg Winkler, Frank Barth, Ram Prasad Gopannagari, Shibly S. Ahmed, Navneet Jain, Atul Kumar Kashyap, Thomas Herrmann, Siddiqi Arif A, James Blatchford, Sushama Davar, Anurag Mittal, Juhan Kim, Jeff Kim, Jens Pika, Michael Zier, Sravan Kumar Tekuru, Siva Krisha Potta, Jamie Schaeffer, Sunil Machha |
| Rok vydání: |
2018 |
| Předmět: |
|
| Zdroj: |
2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM). |
| DOI: |
10.1109/edtm.2018.8421481 |
| Popis: |
A highly optimized 22FDSOI Logic Architecture for Power, Performance, Area (PPA) and cost is presented in this paper. Unique features of FDSOI technology including channel strain based PFET transistor performance enhancement are further advanced with innovative low cost MOL/BEOL based special constructs. The new constructs allow a highly optimized 8T-CNRX library design. Based on this architecture, PPA advantage is demonstrated over competing bulk and FinFET technologies. This Logic Architecture offers FinFET like performance with 28nm bulk like simple MOL and cost structure. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
|
