| Autor: |
Manish S. Patil, Taral D. Chhatbar, Anand D. Darji |
| Rok vydání: |
2010 |
| Předmět: |
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| Zdroj: |
2010 International Conference on Signal Processing and Communications (SPCOM). |
| DOI: |
10.1109/spcom.2010.5560499 |
| Popis: |
A pipelined Fast Fourier Transform and its inverse (FFT/IFFT) processor, which utilizes hardware resources efficiently, is proposed for IEEE standard WiMAX 802.16e. The FFT/IFFT processor is synthesized using UMC 0.18 μm CMOS technology and saves 33% area compared to a conventional implementation approach using radix-2 algorithm without sacrificing system throughput. Proposed Architecture also provides concept of local ROM module, optimized complex multiplier and variable length support from 128-2048 point for FFT/IFFT. Its core size is 2.13 mm × 2.13 mm with 51.25 μs execution time. Its latency is 2050 clock cycle with maximum clock frequency 40 MHz. Start up time for the chip is N/2 clock cycle where N is the length of FFT/IFFT. 16 bit word length with fixed point precision is used for entire implementation. The processor consumes 55.64mW at 40 MHz, 29.13 mW at 20 MHz for length 2048-point and can be Efficiently used for IEEE 802.16e WiMAX standard. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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